projects

PCB placement optimization

Optimization · February – June 2026

Combined greedy initialization, force-directed refinement, and two-stage simulated annealing, with incremental wirelength evaluation and constraint-aware moves.

Reduced half-perimeter wirelength (HPWL) by 31.6%–83.1% across five supplied benchmarks, with zero recorded spacing violations. The largest case contained 115 components and 199 nets.

A five-stage RISC-V CPU

Computer architecture · September – December 2025

Designed an RV32I pipelined CPU in Verilog HDL, including forwarding and stalling logic for data and control hazards. Verified ISA compliance and hardware stability with testbenches in Vivado and ModelSim.

Underwater acoustic direction-of-arrival estimation

Signal processing · September – December 2025

Implemented MUSIC and ESPRIT in MATLAB for high-resolution direction-of-arrival estimation from underwater acoustic arrays, including time-domain spectrum preprocessing for array signals.

Solar lighting controller

Embedded systems · June – July 2025

Built an STM32 controller with PWM charging, constant-voltage / constant-current management, and a 300 mA LED driver. Implemented an OLED battery display, keypad modes, timer-interrupt scheduling, and ADC-based closed-loop sensing using STM32 HAL.