Yifei Gao 高逸飞

UG Visiting Research Student (HKUST) & R&D (WiCi AI) · Supervised by Prof. Zili Meng

• Remote 3DGS training. Kept datasets and training code local while accessing remote GPUs over Wi-Fi. Achieved 83.28% of native training-loop throughput with gsplat, and 82.27% loop / 78.11% end-to-end efficiency with Original 3DGS. The remote setup delivered a 3.26× speedup over a local RTX 4060 with no quality degradation in the reported comparison.
• Metal-to-Vulkan graphics. Developed a compatibility layer with remote rendering and video streaming. GravityMark 1.89 at 1080p, one million particles, and Temporal AA averaged 45.8 application FPS, versus 7.7 FPS on the MacBook Neo’s native Metal path: a 5.95× increase.
• DaVinci Resolve workloads. Translated selected macOS Metal workloads to a remote RTX 5090 Laptop GPU. Exporting 500 frames of Standard Candle UHD: Rocket Science (66 Blur) at 1080p / 25 fps / AV1 took 6m 08s, versus 13m 33s natively on a MacBook Pro M5 Max: 2.21× throughput and 54.7% less export time.

Independent Project · Supervised by Prof. Yiyi Liao

• Inner loop: improve the work. Converts self-review into targeted revisions during research tasks.
• Outer loop: repair the workflow. Uses interface contracts and execution tracebacks to guide workflow repair across a longer research process.
• Pluggable capabilities. Separates task-specific skills from orchestration and recovery logic through a modular architecture.

Student Research Training Program · Project Lead · Supervised by Prof. Jixing Cao

• Foreground-focused reconstruction. Preprocessed training views with a segmentation model so Gaussians were allocated over the foreground. On a consumer RTX 4060, training time fell from 142 to 61 minutes (56.7%), L1 loss fell by 75.2%, and PSNR improved by 0.57 dB in the reported experiment.
• Sparse-view augmentation. Built a hybrid 3DGS–diffusion workflow to augment 8–12 input images before training, evaluating reconstruction across varying structural complexity.

Greedy initialization, force-directed refinement, and two-stage simulated annealing with incremental wirelength evaluation and constraint-aware moves. 31.6%–83.1% less HPWL across five supplied benchmarks, with zero recorded spacing violations. Largest case: 115 components and 199 nets.

Designed an RV32I pipelined CPU in Verilog HDL, with forwarding and stalling logic for data and control hazards. Verified ISA compliance and hardware stability using testbenches in Vivado and ModelSim.

Implemented MUSIC and ESPRIT in MATLAB for high-resolution direction-of-arrival estimation from underwater acoustic arrays. Included time-domain spectrum preprocessing for array signals.

Built an STM32 controller with PWM charging, constant-voltage / constant-current management, and a 300 mA LED driver. OLED battery display, keypad modes, timer-interrupt scheduling, and ADC-based closed-loop sensing using STM32 HAL.